1. Field of the Invention
This invention relates to electronic systems, and more particularly to electrical interconnecting apparatus having two or more electrically connected capacitors.
2. Description of the Related Art
A power distribution network of a typical printed circuit board (PCB) includes several capacitors coupled between conductors used to convey direct current (D.C.) electrical power voltages. For example, the power distribution network of a digital PCB typically includes a bulk decoupling or xe2x80x9cpower entryxe2x80x9d capacitor located at a point where electrical power enters the PCB from an external power supply. The power distribution network also typically includes a decoupling capacitor positioned near each of several digital switching circuits (e.g., digital integrated circuits coupled to the PCB). The digital switching circuits dissipate electrical power during switching times (e.g., clock pulse transitions). Each decoupling capacitor typically has a capacitance sufficient to supply electrical current to the corresponding switching circuit during switching times such that the D.C. electrical voltage supplied to the switching circuit remains substantially constant. The power entry capacitor may, for example, have a capacitance greater than or equal to the sum of the capacitances of the decoupling capacitors.
In addition to supplying electrical current to the corresponding switching circuits during switching times, decoupling capacitors also provide low impedance paths to the ground electrical potential for alternating current (a.c.) voltages. Decoupling capacitors thus shunt or xe2x80x9cbypassxe2x80x9d unwanted a.c. voltages present on D.C. power trace conductors to the ground electrical potential. For this reason, the terms xe2x80x9cdecoupling capacitorxe2x80x9d and xe2x80x9cbypass capacitorxe2x80x9d are often used synonymously.
As used herein, the term xe2x80x9cbypass capacitorxe2x80x9d is used to describe any capacitor coupled between a D.C. voltage conductor and a ground conductor, thus providing a low impedance path to the ground electrical potential for a.c. voltages.
When a desired electrical impedance between a D.C. voltage conductor and a ground conductor is less than the ESR of a single capacitor, it is common to couple more than one of the capacitors in parallel between the D.C. voltage conductor and the ground conductor. In this case, all of the capacitors have substantially the same resonant frequency fres, and the desired electrical impedance is achieved over a range of frequencies including the resonant frequency fres.
When the desired electrical impedance is to be achieved over a range of frequencies broader than a single capacitor can provide, it is common to couple multiple capacitors having different resonant frequencies between the D.C. voltage conductor and the ground conductor. The ESRs and resonant frequencies of the capacitors are selected such that each of the capacitors achieves the desired electrical impedance over a different portion of the range of frequencies. In parallel combination, the multiple capacitors achieve the desired electrical impedance over the entire range of frequencies.
A digital signal alternating between high and low voltage levels includes contributions from a fundamental sinusoidal frequency (i.e., a first harmonic) and integer multiples of the first harmonic. As the rise and fall times of a digital signal decrease, the magnitudes of a greater number of the integer multiples of the first harmonic become significant. As a general rule, the frequency content of a digital signal extends to a frequency equal to the reciprocal of xcfx80 times the transition time (i.e., rise or fall time) of the signal. For example, a digital signal with a 1 nanosecond transition time has a frequency content extending up to about 318 MHz.
All conductors have a certain amount of electrical inductance. The voltage across the inductance of a conductor is directly proportional to the rate of change of current through the conductor. At the high frequencies present in conductors carrying digital signals having short transition times, a significant voltage drop occurs across a conductor having even a small inductance. Transient switching currents flowing through electrical impedances of D.C. power conductors cause power supply voltage perturbations (e.g., power supply xe2x80x9cdroopxe2x80x9d and ground xe2x80x9cbouncexe2x80x9d). As signal frequencies increase, continuous power supply planes (e.g., power planes and ground planes) having relatively low electrical inductances are being used more and more. The parallel power and ground planes are commonly placed in close proximity to one another in order to further reduce the inductances of the planes.
The magnitude of electrical impedance between two parallel conductive planes (e.g., adjacent power and ground planes) may vary widely within the frequency ranges of electronic systems with digital signals having short transition times. The parallel conductive planes may exhibit multiple electrical resonances, resulting in alternating high and low impedance values. High impedance values between power and ground planes are undesirable as transient switching currents flowing through the high electrical impedances cause relatively large power supply voltage perturbations.
Modern computer systems have a requirement for power distribution systems with a low impedance between the power and ground planes over a wide frequency range. Typical target impedances for printed circuit boards in modern computer systems may be on the order of milliohms. The target impedance requirement may extend over a bandwidth that reaches from D.C. up to several gigahertz. At higher frequencies, the size of a printed circuit board may become significant, as the propagation delay associated with the power and ground planes becomes an integral parameter of the power distribution system. Furthermore, printed circuit boards may exhibit resonance peaks in their impedance and EMI (electromagnetic interference) profiles. In some cases, if the separation between the power and ground planes of a printed circuit board is small enough, some of the higher resonant frequencies may be inherently suppressed. However, this still leaves the problem of how to suppress lower resonant frequencies, as well as other frequencies that may occur for various reasons (e.g. power system transients, harmonics associated with clock frequencies, etc.).
Achieving a target impedance over a wide bandwidth using bypass capacitors requires the balancing of capacitance, ESR, and equivalent series inductance (ESL). The challenge of achieving the target impedance over a wide bandwidth is made even more difficult by the fact that capacitance is the only parameter that may be freely chosen. Values of ESL for a given capacitor may be greatly affected by its mounting geometry and dimensions. Values of ESR may be greatly affected by the manufacturing process for a given capacitor. Designers of printed circuit assemblies must take great care in balancing these parameters in order to achieve the desired target impedance over the required bandwidth.
The problems outlined above may in large part be solved by a method for determining the bypass capacitors in order to achieve a target impedance over a wide frequency range. In one embodiment, a power distribution system of an electronic circuit includes at least one pair of planar conductors, including a power plane and a ground plane. The planar conductors may be separated by a dielectric layer. A first capacitor bank may be defined to provide bypassing in a frequency range extending from a maximum frequency down to a first frequency (also referred to as a deviation frequency). The electrical characteristics, or parameters of the first capacitor bank may include a first capacitance, a first resistance, and a first inductance (C10, R10, and L10, respectively). The first capacitance may represent the total capacitance provided by the first capacitor bank, the first resistance may represent the equivalent series resistance (ESR) of the first capacitor bank, and the first inductance may represent the equivalent series inductance (ESL) of the first capacitor bank. The first resistance may be set to be less than or equal to the required target impedance for the frequency range covered by the first capacitor bank. After the characteristics have been defined for the first capacitor bank, a determination may be made for a required effective inductance of a potential second capacitor bank. The second capacitor bank may provide bypassing for a frequency range extending from the first deviation frequency down to a second deviation frequency. In one embodiment, the required effective inductance may be calculated by the formula
L20=a*(C10)*(R10)2.
In this formula, L20 is the required effective of the second capacitor bank, while a is a mathematical constant (which will be explained in further detail below). If the calculation of L20 yields an inductance that is greater than or equal to the output and connection inductance of a connected power source, then there is no need for further capacitor banks. However, if the inductance from the power source is greater than L20, then a second capacitor bank may be necessary. This method may be repeated for additional capacitor banks beyond a second bank until the target impedance requirements are met for all frequency ranges. For example, in determining if a third capacitor bank is required, L30 may be substituted for L20, C20 may be substituted for C10, and R20 may be substituted for R10. Eventually, the power source may be treated as a final capacitor bank with infinite capacitance.
The method may be applied to any type of power distribution structure. Such power distribution structures include those having a pair of planar conductors separated by a dielectric, such as a printed circuit board. The method may also be applied to integrated circuits. In general, the method may be applied to any type of power distribution system wherein capacitors are used for bypassing and/or decoupling. This may include systems without planar conductors.
In one embodiment, the capacitors chosen for each capacitor bank may have a quality factor that is less than 1 (Q less than 1). This may allow the capacitors to provide a target impedance for a wider frequency range. The relationship between bandwidth and quality factor may be expressed as
BW=Fres/Q,
wherein BW is the bandwidth, and Fres is the resonant frequency of the capacitor. The bandwidth may indicate a frequency range over which the impedance of a given capacitor is at or very near its equivalent series resistance. In some instances, if a very low impedance is required for a narrow frequency range, capacitors with a higher value of Q may be selected.
The method described herein may be performed on a computer system. In one embodiment, a computer system may include a processor and a carrier. The carrier may include one or more of the following: DRAM, SRAM, hard disk storage, flash memory, CD-ROM, and digital versatile disk (DVD). The carrier may store instructions that, when executed by the processor, perform an embodiment of the method for determining the decoupling capacitors. The computer system may also include one or more output devices for displaying results to a user.
Thus, in various embodiments, the method for determining the bypass capacitors in order to achieve a target impedance over a wide frequency range may solve the problems outlined above. The method may allow multiple capacitor banks to provide bypassing for both low and high frequencies. Furthermore, since the power source may serve as a final capacitor bank, the quantity of capacitors used may be minimized.